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CD4508BMS
December 1992
CMOS Dual 4-Bit Latch
Pinout
CD4508BMS TOP VIEW
RESET A 1 STROBE A 2 OUTPUT DISABLE A 3 D0A 4 Q0A 5 D1A 6 Q1A 7 D2A 8 Q2A 9 D3A 10 24 VDD 23 Q3B 22 D3B 21 Q2B 20 D2B 19 Q1B 18 D1B 17 Q0B 16 D0B 15 OUTPUT DISABLE B 14 STROBE B 13 RESET B
Features
* High-Voltage Types (20-Volt Rating) * Two Independent 4-Bit Latches * Individual Master Reset for Each 4-Bit Latch * 3-State Outputs with High-Impedance State for Bus Line Applications * Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.) at VDD = 10V and CL = 50pF * 100% Tested for Quiescent Current at 20V * 5V, 10V, and 15V Parametric Ratings * Standardized, Symmetrical Output Characteristics * Maximum Input Current of 1A at 18V Over Full Package Temperature Range; 100nA at 18V and 25oC * Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V * Meets all Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices"
Q3A 11 VSS 12
Functional Diagram
OUTPUT DISABLE D0A Q0A 4-BIT LATCH Q1A 3-STATE OUTUTS Q2A Q3A
Applications
* Buffer Storage * Holding Registers * Data Storage and Multiplexing
D1A D2A D3A STROBE RESET OUTPUT DISABLE D0B D1B D2B D3B STROBE RESET
Description
CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input. The CD4508BMS is supplied in these 24 lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4V H1Z H4P
Q0B Q1B 4-BIT LATCH 3-STATE OUTUTS Q2B Q3B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999
File Number
3337
7-1148
Specifications CD4508BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 15V, No Load VDD = 15V, No Load (Note 3) VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Voltage Low (Note 2) Input Voltage High (Note 2) Tri-State Output Leakage VIL VIH VIL VIH IOZL VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 5V, VOH > 4.5V, VOL < 0.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VDD = 15V, VOH > 13.5V, VOL < 1.5V VIN = VDD or GND VOUT = 0V VDD = 20V VDD = 18V Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3 1 2 3 1 2 3 1, 2, 3 1, 2, 3 1 1 1 1 1 1 1 1 1 7 7 8A 8B 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1 2 3 1 2 3 +25oC, LIMITS TEMPERATURE +25oC +125 C -55oC +25oC +125oC -55oC +25oC +125oC -55oC +125oC, +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +125oC -55oC +25oC +125oC -55oC 3.5 11 -0.4 -12 -0.4 1.5 4 0.4 12 0.4 V V V V A A A A A A -55oC
o
PARAMETER Supply Current
SYMBOL IDD
CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND
MIN -100 -1000 -100 0.53 1.4 3.5 -2.8 0.7
MAX 10 1000 10 100 1000 100 50 -0.53 -1.8 -1.4 -3.5 -0.7 2.8
UNITS A A A nA nA nA nA nA nA mV V mA mA mA mA mA mA mA V V V
+25oC, +125oC, -55oC 14.95
VOH > VOL < VDD/2 VDD/2
3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max.
7-1149
Specifications CD4508BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 260 351 200 270 UNITS ns ns ns ns
PARAMETER Propagation Delay Strobe In to Data Out Transition Time
SYMBOL TPHL1 TPLH1 TTHL TTLH
CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2)
+25oC +125oC, -55oC
NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low Input Voltage High Propagation Delay Strobe In to Data Out VOL VOL VOH VOH IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VIH TPHL1 TPLH1 VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, No Load VDD = 10V, No Load VDD = 5V, VOUT = 0.4V VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V VDD = 15V NOTES 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 3 1, 2, 3 TEMPERATURE -55oC, +25oC +125oC -55oC, +25oC +125oC -55oC, +25oC +125oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC MIN 4.95 9.95 0.36 0.64 0.9 1.6 2.4 4.2 +7 MAX 5 150 10 300 10 600 50 50 -0.36 -0.64 -1.15 -2.0 -0.9 -1.6 -2.4 -4.2 3 140 100 UNITS A A A A A A mV mV V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA V V ns ns
7-1150
Specifications CD4508BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Propagation Delay Data In to Data Out SYMBOL TPHL2 TPLH2 CONDITIONS VDD = 5V VDD = 10V VDD = 15V Propagation Delay Reset to Data Out TPHL3 TPLH3 VDD = 5V VDD = 10V VDD = 15V Propagation Delay 3-State TPHZ TPZH VDD = 5V VDD = 10V VDD = 15V Transition Time 3-State TPLZ TPZL VDD = 5V VDD = 10V VDD = 15V Transition Time Minimum Strobe Pulse Width TTHL TTLH TWS VDD = 10V VDD = 15V VDD = 5V VDD = 10V VDD = 15V Minimum Data Setup Time TS VDD = 5V VDD = 10V VDD = 15V Minimum Data Hold Time TH VDD = 5V VDD = 10V VDD = 15V Minimum Reset Pulse Width TWR VDD = 5V VDD = 10V VDD = 15V Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage SYMBOL IDD VNTH CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A NOTES 1, 4 1, 4 TEMPERATURE +25oC +25oC MIN -2.8 MAX 25 -0.2 UNITS A V CIN Any Input NOTES 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25 C +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC
o o
MIN -
MAX 210 120 90 180 100 80 180 100 70 180 100 70 100 80 140 80 70 50 30 20 0 0 0 200 140 100 7.5
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
1151
Specifications CD4508BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL VTN VTP VTP F CONDITIONS VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC MIN 0.2 VOH > VDD/2 MAX 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS V V V V
ns
NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25oC limit. 4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL IDD IOL5 IOH5A 1.0A 20% x Pre-Test Reading 20% x Pre-Test Reading DELTA LIMIT
TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 IDD, IOL5, IOH5A READ AND RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4
CONFORMANCE GROUPS Group E Subgroup 2
7-1152
Specifications CD4508BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 Note 1 Static Burn-In 2 Note 1 Dynamic BurnIn Note 1 Irradiation Note 2 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 5, 7, 9, 11, 17, 19, 21, 23 5, 7, 9, 11, 17, 19, 21, 23 5, 7, 9, 11, 17, 19, 21, 23 GROUND 1-4, 6, 8, 10, 12-16, 18, 20, 22 12 1, 3, 12, 13, 15 12 VDD 24 1-4, 6, 8, 10, 1316, 18, 20, 22, 24 2, 14, 24 1-4, 6, 8, 10, 1316, 18, 20, 22, 24 5, 7, 9, 11, 17, 19, 21, 23 4, 6, 8, 10, 16, 18, 20, 22 9V -0.5V 50kHz 25kHz
Logic Diagram
OUTPUT DISABLE TYPICAL LATCH OUTPUT DISABLE VDD
3 OUTPUT DISABLE - A 1
*
*
ST p n VSS ST ST ST p VDD Qn-A 5(7, 9, 11) OUTPUT
RESET - A 4(6, 8, 10) Dn - A
*
2
*
ST
n ST VSS
STROBE - A
* All inputs protected by CMOS protection network. FIGURE 1. LOGIC DIAGRAM (A-SECTION), 1 OF 4 IDENTICAL LATCHES WITH COMMON OUTPUT DISABLE, RESET AND STROBE TRUTH TABLE RESET 0 0 0 1 X 1 = HIGH LEVEL 0 = LOW LEVEL DISABLE 0 0 0 0 1 STROBE 1 1 0 X X D INPUT 1 0 X X X Q OUTPUT 1 0 LATCHED 0 Z
X = DON'T CARE Z = HIGH IMPEDANCE
7-1153
CD4508BMS Typical Performance Characteristics
OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
30 25 20 15 10 5
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 7.5 5.0 2.5 10V
10V
5V 0 5 10 15
5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5
0
0 -5 -10 -15
0
0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 100
-10V
-20 -25
-10V
-10
-15V
-30
-15V
-15
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
PROPAGATION DELAY TIME (tPHL, tPLH) - ns AMBIENT TEMPERATURE (TA) = +25oC 175 150 125 100 75 10V 50 25 15V
AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (fTHL, fTLH) (ns)
200 SUPPLY VOLTAGE (VDD) = 5V
SUPPLY VOLTAGE (VDD) = 5V
150
100 10V 50 15V
0 0
20
40 60 80 100 LOAD CAPACITANCE (CL) (pF)
0
20
40 60 80 LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE
FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (STROBE TO DATA OUT)
7-1154
CD4508BMS Typical Performance Characteristics
105
8 6 4
POWER DISSIPATION PER 4-BIT LATCH (PD) - W
(Continued)
2
AMBIENT TEMPERATURE (TA) = +25oC, tr, tf = 20ns RL = 200k SUPPLY VOLTAGE (VDD) = 15V 10V 10V 5V
104
8 6 4
103
2 8 6 4 2
102
8 6 4 2
CL = 50pF CL = 15pF
2 4 68 2 4 68 2 4 68 2 4 68
10 10 101 103 102 INPUT FREQUENCY (fIN) (kHz) 104
FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY
Waveforms and Test Circuits
tW(st) STROBE INPUT tSU tH Dn INPUT tW(R) RESET OUTPUT DISABLE
tPLH Qn OUTPUT tTLH
tPHL tPHL
tPLH
tTHL
FIIGURE 9. TEST WAVEFORMS
VDD VDD 50% OUTPUT DISABLE tPLZ STROBE DISABLE D0 D1 D2 D3 RESET Q0 Q1 Q2 50pF Q3 CHAR. tPHZ VSS tPLZ tPZL tPZH TEST ANY OUTPUT 1k Q tPHZ Q OUTPUT Q OUTPUT 10% 90% 10% tPZH TEST VOLT. AT D VDD VSS VSS VDD AT Q VSS VDD VDD VSS 50% VSS tPLZ 90% VDD VOL VOH VSS
PULSE GEN D
FIGURE 10. OUTPUT DISABLE TEST CIRCUIT AND WAVEFORMS
7-1155
CD4508BMS Bus Registers
CD4508BMS 3-STATE 4 BIT LATCH 3-STATE 4 BIT LATCH CD4508BMS DATA BUS
4-LINE DATA BUS RESET CLOCK 4-LINE DATA BUS CD4019BMS
SERIAL DATA
4 BIT SHIFT REGISTER
4 BIT SHIFT REGISTER
CD4015BMS
3-STATE 4 BIT LATCH STROBE
3-STATE 4 BIT LATCH
A B
DISABLE DISABLE 4-LINE DATA BUS
QUAD LATCH (3 STATE)
QUAD LATCH (3 STATE)
CD4508BMS
FUNCTON SELECT A 0 1 0 1 B 0 0 1 1 FUNCTION Inhibit (All 0) Select A Bus Select B Bus AI + BI
FIGURE 11. BUS REGISTER
FIGURE 12. DUAL MULTIPLEXED BUS REGISTER WITH FUNCTION SELECT
Chip Dimensions and Pad Layouts
0 94 90 80 70 60 50 40 30 20 10 0 4-10 (0.102-0.254) 93-101 (2.362-2.565) 91-99 (2.311-2.515) 10 20 30 40 50 60 70 80 90 96
Dimensions in parentheses are in milimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch.)
METALLIZATION: PASSIVATION:
Thickness: 11kA - 14kA,
AL.
10.4kA - 15.6kA, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1156

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